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a 140 msps graphics digitizer preliminary technical data 1/27/ 99 ad9884 rev. pra analog devices, inc., 1999 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. one technology way, p.o box 9106, norwood, ma 02062?9106, usa tel: 617/329?4700 fax: 617?326?8703 the ad9884 is a complete 8-bit 140msps, monolithic graphics digitizer optimized for digitizing rgb graphics signals from personal computers and workstations. its 140msps encode rate capability and full-power analog bandwidth of 500mhz supports display resolutions of up to 1280 x 1024 at 75hz with sufficient input bandwidth to accurately acquire and digitize each pixel. to minimize system cost and power dissipation, the ad9884 includes an internal +1.25v reference, pll to generate a pixel clock from hsync and coast, and programmable gains, offset, and clamp control. the user provides only a +3.3v power supply, analog input, and hsync and coast signals. three-state cmos outputs may be powered from 2.5v to 3.3v. the ad9884?s on-chip pll generates a pixel clock from hsync and coast inputs. pixel clock output frequencies range from 20 to 140 mhz. pll clock jitters is 500ps p-p typical relative to the input reference. when the coast signal is presented, the pll maintains its output frequency in the absence of hsync. a sampling phase adjustment is provided. data, hsync and clock output phase relationships are maintained. the pll can be disabled and external clock input provided as the pixel clock. a clamp signal is generated internally or may be provided by the user through the clamp input pin. this device is fully programmable via a two wire serial port. fabricated in an advanced cmos process, the ad9884 is provided in a space-saving 128-lead mqfp surface mount plastic package and is specified over the 0c to +85c temperature range. features 140 msps maximum conversion rate 500 mhz analog bandwidth 0.5v to 1.0v analog input range 500ps p-p pll clock jitter 3.3v power supply 2.5v to 3.3v three-state cmos outputs demultiplexed output ports data clock output provided low power: 730mw typical internal pll generates clock from hsync serial port interface fully programmable supports 2 pixels per clock mode applications rgb graphics processing lcd monitors and projectors plasma display panels scan converters clamp a/d r ain r outa r outb 8 8 8 clamp a/d g ain g outa g outb 8 8 8 clamp a/d b ain b outa b outb 8 8 8 clock generator hsync coast ckinv ckext datack filt control ref. sda scl a 0 pwrdn/ a 1 refout hsout datack/ clamp generator clamp refin pll hs pxck adcck
ad9884 ad9884 preliminary technical data ? 1/27/99 ? 2 ?. critical characteristics (v d = +3.3v, v dd = +3.3v, adc clock = maximum conversion rate test ad9884kst-140 ad9884kst-100 parameter temp level min typical max min typical max units resolution 8 8 bits dc accuracy differential nonlinearity +25c full i vi 0.5 0.9 0.5 0.9 lsb lsb integral nonlinearity +25c full i vi 0.5 0.9 0.5 0.9 lsb lsb no missing codes full vi guaranteed guaranteed gain tempco full v tbd tbd ppm/c analog input input voltage range full v 0.5 1.0 0.5 1.0 v p?p input resistance +25c i tbd tbd k w full vi tbd tbd k w input capacitance +25c v 4 4 pf input bias current +25c full i vi tbd tbd tbd tbd m a m a hsync input range full v 30 90 30 90 khz analog bandwidth, full power +25c v 500 500 mhz reference output output voltage full vi +1.25 +1.25 v temperature coefficient full v 50 50 ppm/c switching performance maximum conversion rate full vi 140 100 msps minimum conv ersion rate full iv 20 20 msps data to clock skew full vi tbd tbd ns digital inputs input capacitance +25 c v 3 3 pf digital outputs logic "1" voltage full vi v d -0.1 v d -0.1 v logic "0" voltage full vi 0.1 0.1 v output coding binary binary power supply v d supply current full vi 180 180 ma v dd supply current full vi 40 40 ma total power dissipation full vi 730 730 mw powerdown supply current full vi tbd tbd ma powerdown dissipation full vi tbd tbd mw dynamic performance transient response +25c v 2 2 ns overvoltage recovery time +25c v 1.5 1.5 ns signal?to?noise ratio (snr) (without harmonics) f in = 19.7 mhz +25c full i v 46 45 46 45 db db signal?to?noise ratio (sinad) (with harmonics) f in = 19.7 mhz +25c full i v 45 44 45 44 db db effective number of bits f in = 19.7 mhz +25c i 7.2 7.2 bits crosstalk full v 55 55 dbc
ad9884 rev. pra ? 3 ? ad9884 preliminary technical data ? 1/27/99 ordering guide model temperature range package option ad9884ks-140 AD9884KS-100 ad9884/pcb 0c to +85c 0c to +85c +25c st-128 st-128 evaluation board explanation of test levels test level i 100% production tested. ii 100% production tested at +25c and sample tested at specified temperatures. iii sample tested only. iv parameter is guaranteed by design and characterization testing . v parameter is a typical value only. vi 100% production tested at +25c; guaranteed by design and characterization testing. absolute maximum ratings * v d ................................ ................................ ........................ +4 v v dd ................................ ................................ ...................... +4 v analog inputs ................................ ............................. v d to 0.0 v vref in ................................ ................................ ..... v d to 0.0 v digital inputs ................................ .............................. v d to 0.0 v digital output current ................................ ....................... 20 ma operating temperature ................................ ............ 0c to +85 c storage temperature ................................ .......... ?65c to +150 c maximum junction temperature ................................ ...... +175 c maximum case temperature ................................ ............ +150 c stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions outside of those indicated in the operation sections of this specification is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability.
ad9884 ad9884 preliminary technical data ? 1/27/99 ? 4 ?. serial port register address list. note: all data is assumed to be loaded msb first. hex address bits register name function 00h 7:0 pll div msb this register is for bits [11:4] of the pll divider. larger values mean the pll operates at a faster rate. this register should be loaded first whenever a change is needed (this will give the pll more time to lock.) 01h 7:4 pll div lsb bits [3:0] of the msb divider word 02h 7:0 red gain controls adc input range (contrast) of each respective channel. smaller values give more contrast. 03h 7:0 green gain 04h 7:0 blue gain 05h 7:2 red offset controls dc offset (brightness) of each respective channel. smaller values give a brighter image. 06h 7:2 green offset 07h 7:2 blue offset 08h 7:0 clamp placement places the clamp signal an integer number of clock periods after the trailing edge of the hsync signal (see control register bit 3 description). 09h 7:0 clamp duration number of clock periods that the clamp signal is actively clamping. 0ah 7:1 control bit 7 ? channel mode. determines single channel or dual channel output mode. (logic 0 selects single channel mode.) bit 6 ? output mode. determine interleaved or parallel output mode. (logic 0 selects interleaved mode.) bit 5 ? hsync polarity. changes polarity of incoming hsync signal. (logic 1 selects active high.) bit 4 ? coast polarity. changes polarity of external coast signal. (logic 1 selects active high) bit 3 ? clamp function. chooses between hsync for clamp signal or another external signal to be used for clamping. (logic 0 chooses hsync). bit 2 ? clamp polarity. valid only with external clamp signal. logic 1 selects active low. bit 1 ? pll bypass. shuts down pll and allows external clock to drive the part. (logic 1 selects bypassing of the internal pll.) 0bh 7:3 phase adjust adc clock phase adjustment. larger values mean more delay. (1lsb=t/32) 0ch 7:2 vco/cpmp bit 7 ? must be set to 0 for proper device operation. bits [6:5] vco range. selects vco frequency range. (see pll description) bits [4:2] charge pump current. varies the current that drives the low pass filter. (see pll description) 0dh test register reserved for future use
ad9884 rev. pra ? 5 ? ad9884 preliminary technical data ? 1/27/99 serial port default values register name default value pll divider 1693 red gain 128 green gain 128 blue gain 128 red offset 32 blue offset 32 green offset 32 clamp placement 128 clamp duration 128 control channel mode 1 (dual channel mode) output mode 1 (parallel) hsync polarity 1 (active high) coast polarity 1 (active high) clamp function 0 (clamp derived from hsync) clamp polarity 1 (active low) pll bypass 0 (pll active) phase adjust 16 bit 7 0 vco/cpmp vco range 1 charge pump current 1 the serial port address for the ad9884 is 10011 xx0.
ad9884 ad9884 preliminary technical data ? 1/27/99 ? 6 ?. ad9884 application diagram 28 1 9 10 12 13 14 15 16 17 18 19 20 21 24 23 22 2 3 4 6 5 7 8 11 25 26 27 29 30 35 34 33 32 31 38 37 36 75 102 94 93 91 90 89 88 87 86 85 84 83 82 79 80 81 101 100 99 97 98 96 95 92 78 77 76 74 73 68 69 70 71 72 65 66 67 108 116 115 112 113 114 111 110 109 107 106 103 104 105 117 118 128 127 125 124 123 122 121 120 119 126 50 49 39 40 42 43 44 45 46 47 48 41 59 51 52 55 54 53 56 57 58 60 61 64 63 62 nc nc nc v d gnd gnd r ain v d gnd v d v d pin 1 identifier g ain gnd gnd gnd v d v d gnd v d gnd gnd b ain v d gnd v d gnd ckinv clamp sda scl a 0 a 1 pv d pv d gnd nc nc nc v dd v dd gnd gnd v dd gnd gnd gnd gnd v d v dd pwrdn/ datack datack/ hsout nc refout refin v d hsync gnd pv d ckext filt coast gnd nc gnd pv d pv d gnd gnd v dd gnd gnd d b b 7 d b b 6 d b b 5 d b b 4 d b b 3 d b b 2 d b b 1 d b b 0 gnd d r a 7 d r a 6 d r a 5 d r a 4 d r a 3 d r a 2 d r a 1 d r a 0 gnd v dd v dd gnd gnd v dd d b a 7 d b a 6 d b a 5 d b a 4 d b a 3 d b a 2 d b a 1 d b a 0 d g b 7 d g b 6 d g b 5 d g b 4 d g b 3 d g b 2 d g b 1 d g b 0 d g a 7 d g a 6 d g a 5 d g a 4 d g a 3 d g a 2 d g a 1 d g a 0 d r b 7 d r b 6 d r b 5 d r b 4 d r b 3 d r b 2 d r b 1 d r b 0 0.1 m f 50nf 75 w 50nf 75 w 50nf 75 w v d 4.7k w 4.7k w 0.01 m f 1.5k w 0.18 m f p v d 10k w v dd ad9884 top view (pins down)
ad9884 rev. pra ? 7 ? ad9884 preliminary technical data ? 1/27/99 pin number name function 1,2,3,36,37,38,46,118 nc no connect (leave floating) 5,6,9,12,13,14,17,20,21,24,26,35,39,42,47,49, 51,52 53,63,73,83,93,103,113,119,121,122,123 gnd ground 4,8,10,11,16,18,19,23,25,124,128 v d converter power supply (nominally 3.3v) 7 r ain analog input for converter r 15 g ain analog input for converter g 22 b ain analog input for converter b 27 ckinv invert sample clock input (2 pixels/clock mode) 28 clamp clamp input(external clamp signal) 29 sda serial port serial data input 30 scl serial port serial data clock (400khz maximum) 31 a 0 serial port address input 1 32 a 1 serial port address input 2 33,34,43,48,50 pv d pll power supply (nominally 3.3v) 40 hsync horizontal sync input 41 coast pll coast signal input 44 ckext external pixel clock input (to bypass internal pll) or 10k w to v dd 45 filt connection for external filter components for internal pll 54,64,74,84,94,104,114,120 v dd output power supply (nominally 3.3v) 55-62 d b b 7 -d b b 0 digital outputs of converter ?b?, channel b. d b b 7 is the msb. 65-72 d b a 7 -d b a 0 digital outputs of converter ?b?, channel a. d b a 7 is the msb. 75-82 d g b 7 -d g b 0 digital outputs of converter ?g?, channel b. d g b 7 is the msb. 85-92 d g a 7 -d g a 0 digital outputs of converter ?g?, channel a. d g a 7 is the msb. 95-102 d r b 7 -d r b 0 digital outputs of converter ?r?, channel b. d r b 7 is the msb. 105-112 d r a 7 -d r a 0 digital outputs of converter ?r?, channel a. d r a 7 is the msb. 115 datack data output clock 116 datack/ data output clock compliment 117 hsout hsync output clock (phase-aligned with datack and datack/) 125 pwrdn/ power down and three state output control (active low) 126 refout internal reference output (bypass with .1f to ground) 127 refin reference input (+1.25v +/- 10%) application diagram notes: 1) all supply pins (v d and v dd ) should be bypassed to the adjacent gnd pin using 0.1uf chip capacitors as close to the pins as possible. 2) all gnd pins should be tied to one common ground plane. 3) the user may consider making allowances to insert a series resistor in the data path (close to the ad9884) for additional isolation.
ad9884 ad9884 preliminary technical data ? 1/27/99 ? 8 ?. timing diagrams the following timing diagrams show the operation of the ad9884 in all clock modes. the part establishes timing by having the sample that corresponds to the pixel digitized when the leading edge of hsync occurs sent to the ?a? data port. in dual channel mode, the next sample is sent to the ?b? port. future samples are alternated between the ?a? and ?b? data ports. in single channel mode, data is only sent to the ?a? data port. the output data clock signal is created so that it?s rising edge always occurs between ?a? data transitions, and can be used to latch the output data externally. the hsync output is pipelined with the data in a fixed timing relationship between the two in all single channel modes (four data sets are presented before valid data is available) and in all dual channel modes (two data sets are presented before valid ?a? port data is available). in 2 pixels/clock modes, ?even? pixels represent samples taken on the rising edge of the pixel clock (pxck). ?odd? pixels represent samples taken on the falling edge of pxck. 1. single channel mode p0 p1 p2 p3 p4 p5 p6 p7 rgbin hsync pxck adcck datack douta hs hsout d0 d1 d2 d3 d4 d5 d6 d7 5 pipe delay
ad9884 rev. pra ? 9 ? ad9884 preliminary technical data ? 1/27/99 2. single channel mode, 2 pixels/clock (even pixels) rgbin hsync pxck adcck datack douta d0 d2 d4 d6 p0 p1 p2 p3 p4 p5 p6 p7 5 pipe delay hs hsout 3. single channel mode, 2 pixels/clock (odd pixels) rgbin hsync pxck 5.5 pipe delay adcck datack douta d7 d1 d3 d5 p0 p1 p2 p3 p4 p5 p6 p7 hs hsout
ad9884 ad9884 preliminary technical data ? 1/27/99 ? 10 ?. 4. dual channel mode, interleaved outputs p0 p1 p2 p3 p4 p5 p6 p7 rgbin hsync pxck 5 pipe delay adcck datack douta doutb d3 d5 d7 d0 d2 d4 d6 d1 hs hsout 5. dual channel mode, parallel outputs p0 p1 p2 p3 p4 p5 p6 p7 rgbin hsync pxck 6 pipe delay adcck datack douta doutb d2 d4 d6 d1 d3 d5 d7 d0 hs hsout
ad9884 rev. pra ? 11 ? ad9884 preliminary technical data ? 1/27/99 6. dual channel mode, interleaved outputs, 2 pixels/clock (even pixels) rgbin hsync pxck adcck datack douta doutb d4 d2 d6 p0 p1 p2 p3 p4 p5 p6 p7 5 pipe delay d0 hs hsout 7. dual channel mode, interleaved outputs, 2 pixels/clock (odd pixels) rgbin hsync pxck adcck datack douta doutb p0 p1 p2 p3 p4 p5 p6 p7 d3 d7 d1 d5 5.5 pipe delay hs hsout
ad9884 ad9884 preliminary technical data ? 1/27/99 ? 12 ?. 8. dual channel mode, parallel outputs, 2 pixels/clock (even pixels) rgbin hsync pxck adcck datack douta doutb p0 p1 p2 p3 p4 p5 p6 p7 d2 d6 d0 d4 6 pipe delay hs hsout 9. dual channel mode, parallel outputs, 2 pixels/clock (odd pixels) rgbin hsync pxck 6.5 pipe delay adcck datack douta doutb p0 p1 p2 p3 p4 p5 p6 p7 d5 d1 d7 d3 hs hsout
ad9884 rev. pra ? 13 ? ad9884 preliminary technical data ? 1/27/99 loop natural frequency w n = ; w z = clamp the clamp signal is generated internally, or by the user through the clamp input pin. a 1-bit register loaded through the serial port controls the option of internal or external clamp. the polarity of the input clamp signal is programmable (also controlled by a 1-bit register loaded through the serial port.) external digital adjustment of the placement and duration of the clamp signal is controlled by two on-chip 8-bit registers. leading edge placement of the internally generated clamp signal is relative to the trailing edge of hsync. the duration is relative to the leading edge of the generated clamp signal. the circuit contains two 8-bit counters clocked by the adc clock, so 1 lsb of either placement or duration resolution is equal to a single adc clock period. gain control the ad9884 has an analog input range of 0.5v to 1.0v. gain on each channel is digitally adjustable through the 8-bit register. a gain setting of ?0? corresponds to the minimum analog input range (0.5v p-p or less). a gain setting of 255 corresponds to the maximum analog input range (1v p-p or more). offset control each adc channel is digitally adjustable for offset control through a 6-bit on-chip register. 1 lsb of offset equals 1 adc lsb. an offset code setting of 31 means approximately zero offset. an offset setting code of 0 means approximately ?31 codes of offset, and an offset setting of 63 means approximately 32 codes of offset at the adc outputs. phase-locked loop the pll generates the appropriate pixel clock frequency from the incoming hsync signal. it is possible to bypass the pll, providing the pixel clock externally through the ckext pin. whether the pixel clock is taken from the pll or the 1-bit pll bypass register controls the ckext pin. setting pll bypass to `1' bypasses the pll. if the pixel clock is being provided externally, the pll is powered off. an external low pass loop filter must be provided for the pll to operate. this filter, which is connected to the filt pin, is shown below with the required component values. the loop filter component values together with charge pump current values serve to set the loop bandwidth and loop- damping coefficients. the loop equations for these parameters are 1.5k w 0.18 m f 0.01 m f pv d filt c p c z r z )n c (c i k p z p vco + z z c r 1 loop damping factor = z n 2 1 w w . loop stability is achieved if w n < 10 in w
ad9884 ad9884 preliminary technical data ? 1/27/99 ? 14 ?. four programmable registers are provided to optimize the performance of the pll. these registers are: (1) the 12-bit divisor register. the input hsync frequencies range from 30 khz to 90 khz. the pll multiplies the frequency of the hsync signal, producing output signal frequencies in the range of 20 mhz to 140 mhz. the divisor register controls the exact multiplication factor. this register may be set to any value between 221 and 4095. (the divide ratio that is actually used is the programmed divide ratio plus one.) (2) the 3-bit vco range register. to lower the sensitivity of the output frequency to noise on the control signal, the vco operating frequency range is divided into four overlapping regions. the vco range register sets this operating range. because there are only four possible regions, only the two least-significant bits of the vco range register are used. the frequency ranges for the lowest and highest regions are shown in table 1. table 1: vco frequency ranges pv2 pv1 pv0 range k vco (gain mhz/v) 1 0 0 20-60 mhz 100 mhz/v 1 0 1 50-90 mhz 100 mhz/v 1 1 0 80-120 mhz 135 mhz/v 1 1 1 110-140 mhz 160 mhz/v (3) the 3-bit pump current range register. this register allows the current that drives the low pass loop filter to be varied. the possible current values are listed in table 2. table 2: charge pump current/control bits ip2 ip1 ip0 current ( m a) 0 0 0 50 0 0 1 100 0 1 0 150 0 1 1 250 1 0 0 350 1 0 1 500 1 1 0 750 1 1 1 1500 (4) the 5-bit phase adjust register. the phase of the generated sampling clock may be shifted to locate an optimum sampling point within a clock cycle. the phase adjust register provides 32 phase-shift steps of 11.25 degrees each. the hsync signal with an identical phase shift is available through the hsout pin. phase adjustment is still available if the pixel clock is being provided externally. the coast pin is used to allow the pll to continue to run at the same frequency, in the absence of the incoming hsync signal. this may be used during the frame flyback, or any other time that the hsync signal is unavailable. the polarity of the coast signal may be set through the coast polarity register. also, the polarity of the hsync signal may be set through the hsync polarity register. for both hsync and coast, a value of `1' inverts the signal. 2 pixels/clock mode logic 1 input on ckinv (pin 27) inverts the nominal adc clock. clock invert can be switched between frames to implement the 2 pixels/clock mode function. this allows higher effective image resolution to be achieved at lower pixel rates but with lower frame rates.
ad9884 rev. pra ? 15 ? ad9884 preliminary technical data ? 1/27/99 (64 codes) input range offset range v off (64 codes) 1 v 0 v input range offset range v off (64 codes) .5 v 0 v adc block diagram (single channel output) relationship of offset range to input range in c l a m p 8 x1.2 offset 8 6 gain v off ref dac dac adc
ad9884 ad9884 preliminary technical data ? 1/27/99 ? 16 ?.

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